Non-volatile memory (NVM) is a memory device that retains content stored therein even when power is removed. EEPROM and flash memory are two commonly used non-volatile memory devices. In particular, flash memory has become widely used in electronic devices, especially portable electronic devices, because of its ability to provide data storage at low power levels. Modern day flash memory devices are typically implemented using a floating gate MOS transistor device as the memory cells. Charge storage on the floating gate determines the stored data state (“0” or “1”) of the memory cell.
In a non-volatile memory cell implemented using a floating gate MOS device, programming of the memory cell, or writing data to the memory cell, is accomplished by transferring charge carriers from the semiconductor substrate (the source or the drain) to the floating gate by tunneling through the thin gate oxide layer. Typically, a block of non-volatile memory cells is first erased by applying bias conditions to remove the charges stored on the floating gate. Then, the non-volatile memory cells can be written or programmed, usually one byte or word at a time, by applying the bias conditions opposite to the erase operation. Erase and programming operation of non-volatile memory devices require a relatively large voltage and current.
Flash memory devices constructed using an NMOS double poly flash memory cell have been widely adopted. In a NMOS double poly flash memory cell, a floating gate is formed between a control gate and the channel region (the substrate) of the MOS device and the floating gate is at least partially vertically aligned with the control gate. While the NMOS double poly flash memory cell architecture has been wide applied, the double poly flash memory cell requires special fabrication process to form the two polysilicon layers and is therefore not compatible with standard logic CMOS fabrication processes which often include only a single polysilicon layer.
Multi-time programmable (MTP) flash memory devices that can be fabricated using standard logic CMOS fabrication processes are favored for reduction in manufacturing cost by eliminating the expensive double poly fabrication process. These single polysilicon MTP flash memory cells can be advantageously applied in embedded applications. For example, a PMOS MTP flash memory cell can be formed using a two-transistor cell, including a floating gate, a select gate and a control gate formed in a P-well and capacitively coupled to the floating gate. The PMOS MTP flash memory cell stores charges on the floating gate and support multiple write cycles. PMOS MTP flash memory cells constructed using standard logic CMOS fabrication processes have been shown to provide more than 10-year retention time after one hundred thousand program and erase cycles in system application.
In general, PMOS MTP flash memory cells are programmed using gate induced drain leakage (GIDL). However, there are some limitations with programming of PMOS MTP flash memory cells using GIDL current. First, when the MTP flash memory cells are fabricated using standard logic CMOS processes, the logic transistors are often designed for low power supply voltage (e.g. 1V) and the logic transistors are formed with lightly-doped drain junction structure on the source/drain regions which disturb the GIDL current for programming. Second, the vertical electric field across the thin gate oxide is often not very strong. Accordingly, in some designs, PMOS MTP flash memory cells are programmed using hot carrier injection (HCI). However, when HCI is used for programming, the cell current increases as the programming of the memory cell progresses. With the large cell current during programming (e.g. greater than 80 μA per cell), it is often not possible to perform programming of a byte of data at the same time as device specification often requires low power consumption at low power supply voltage. The programming speed becomes very slow when bit-by-bit programming is used to reduce power consumption.